ML for Hardware

This project focuses on developing ML-driven solutions for Electronic Design Automation (EDA) to enhance verification, synthesis, and place-and-route. By leveraging AI, it aims to accelerate verification through GPU-accelerated SAT sampling, optimize synthesis with learning-based techniques, and improve place-and-route using data-driven heuristics that adapt to circuit constraints. Integrating machine learning into these traditionally heuristic-driven processes enhances efficiency, scalability, and automation, enabling faster and more reliable hardware design.

Differential and Massively Parallel Sampling of SAT Formulas (Arash Ardakani, Minwoo Kang, Kevin He, Vighnesh Iyer, Suhong Moon, John Wawrzynek, DAC 2024)

DEMOTIC: A Differentiable Sampler for Multi-Level Digital Circuits (Arash Ardakani, Minwoo Kang, Kevin He , Qijing Huang, Vighnesh Iyer, Suhong Moon, John Wawrzynek, ASP-DAC 2025 (To appear))

High-Throughput SAT Sampling (Arash Ardakani, Minwoo Kang, Kevin He, Qijing Huang, John Wawrzynek, DATE 2025 (To appear))

Recurrent CircuitSAT Sampling for Sequential Circuits (Arash Ardakani, Kevin He, John Wawrzynek, Under-review)